Field of the Invention
The present invention relates in general to the process of issuing and dispatching instructions in a microprocessor, and more particularly to a fused reservation stations module that dispatches instructions for execution by the microprocessor more efficiently and with improved performance.
Description of the Related Art
Many modern microprocessors are superscalar in which they include multiple execution units and are capable of dispatching multiple instructions to the execution units in a single clock cycle. Many modern microprocessors also perform out-of-order (O-O-O) execution. That is, the microprocessor may execute instructions out of the order specified by the instructions of the software program. Superscalar out-of-order execution microprocessors typically attempt to maintain a relatively large pool of outstanding instructions so that they can take advantage of a larger amount of instruction parallelism.
A microprocessor executes the instructions of a corresponding instruction set architecture, such as the x86 instruction set architecture or the like. In many such microprocessors, the instructions of the instruction set architecture, often referred to as macroinstructions, are first translated into microinstructions (or micro-operations or “μops”) that are issued to a reservation stations module, which in turn dispatches the instructions to the execution units. The microinstructions are more generally referred to herein simply as the instructions. The instructions are also issued to a reorder buffer (ROB) which ensures in-order retirement of the instructions.
The reservation stations (RS) include one or more ordered queues. When there are multiple instructions that are ready for dispatch from an RS queue, meaning that the instructions have met the conditions for being dispatched to an execution unit, then one or more of the ready instructions are dispatched to corresponding execution units. An instruction is ready for dispatch when an execution unit is available and when any operands necessary for instruction execution are also available. The efficiency and performance of the RS both need to improve as microprocessor design becomes increasingly more complex. It is desired to improve the timing and throughput of the RS by making it smaller and more efficient. The RS should also provide greater entry efficiency and increased execution unit support. Conventional RS configurations do not meet all of these design improvement goals.